The present invention relates to power consumption in digital circuitry such as microprocessors, counters and the like. It relates to a method of decreasing the power consumption of a digital circuit which is controlled by clock signals by using a transfer gate composed of metal oxide semiconductor transistors and by stopping the clock.
In complementary metal oxide semiconductor (CMOS) circuits, transistors are typically arranged in complementary pairs. Because only one of these complementary pairs of transistors is usually conducting at a time, the pair as a whole presents a large resistance to the power source and such circuits consume small amounts of power during most of the time they are operating. In CMOS circuits, most of the power is consumed during switching operations when each of the complementary pair of transistors might be conducting at the same time. Consequently the power consumption of a CMOS circuit can be decreased by stopping the clock signal and hence interrupting the switching.
The following is a description of a conventional CMOS circuit, as found in the prior art, capable of decreasing the current consumption by stopping the clock. FIG. 1 is a state transition diagram showing the operation of a digital circuit. In FIG. 1,1, S2 and S3 represent three states of the circuit. S1 corresponds to state A, S2 to state B, and S3 to state C. S4-S9 represent transitions of the circuit from one state to another.
FIG. 6 is a circuit diagram of a particular three-state circuit whose transition diagram might be represented by FIG. 1. FIG. 6 is a CMOS circuit using a two-phase clock according to the prior art. In FIG. 6, numerals 10-15 are D latches, 16 and 17 are master slave flip-flops, 18-20 are logic circuits, 21 and 22 are input signal lines for supplying the input signals I.sub.1 and I.sub.2, 23 and 24 are clock signal lines for supplying the first clock signal phi.sub.1 and the second clock signal phi.sub.2, and 25 is a reset signal line for supplying a reset signal.
Each D latch and flip-flop in FIG. 6 is composed of CMOS transfer gates 26 and 27 in combination with signal value holding circuits 30 and 31 which use transfer gates 28 and 29 as shown in FIG. 7. The digital circuit shown in FIG. 6 includes subcircuits 44-46, which themselves include logic circuits 18-20 responsive to input signals I.sub.1 and I.sub.2. A set of transfer gates shown as D latches 10-12 are provided at the output of the logic circuits 18-20. The transfer gates 10-12 open during the pulses of the clock signal phi.sub.1. A second set of transfer gates, D latches 13-15, are installed at the input of the logic circuits, and the output of the first set of transfer gates is fed back to the input of the second set of transfer gates through feed back loops. The second set of transfer gates is operated by a second clock signal phi.sub.2.
The states of the circuit is defined by the output values of the first transfer gates. The state to which the circuit moves at the next assertion of the clock pulses is determined by the configuration of the circuit, which comprise the state of the circuit and the values asserted at the inputs. The set of all possible configurations may be classified into two categories. One of the categories are the stoppable configurations, in which the input signals I.sub.1 and I.sub.2 are such that succeeding clock pulses will not lead to a change of state. The other categories are the temporary configurations, in which succeeding clock pulses do lead to a change of state of the circuit.
As shown by the transition diagram in FIG. 1, the circuit has three states: state A (S1); state B (S2); and state C (S3). The circuit responds to a reset signal R, input signal I.sub.1 and a second input signal I.sub.2. The changes of state are shown by the transition diagram as follows:
1. If the reset signal R is high, the circuit enters state A (S4);
2. If the input signal I is high when the circuit is in state A and the reset signal R is low, the circuit enters state B upon the arrival of the next clock pulse phi.sub.1. If I.sub.1 is low, the circuit remains in state A (S6);
3. When the circuit is in state B, and the reset signal R is low, the circuit enters state C upon the arrival of the next clock pulse phi.sub.1 (S7); and
4. If the input signal I.sub.2 is high when the circuit is in state C and the reset signal R is low, the circuit enters state A with the arrival of the next clock pulse phi (S8). If input signal I.sub.2 is low, the circuit remains in state C (S9).
For the circuit shown in FIG. 6, the three states are defined by the outputs of the D latches. State A is defined as when D latch 10 is high, state B is defined as when D latch 11 is high and state C is defined as when D latch 12 is high. D latches 10-12 open during the pulses of the first clock signal phi.sub.1, and the D latches 13-15 fetch the values of D latches 10-12 during the pulses of the second clock signal phi.sub.2. The input signals I.sub.1 and I.sub.2 are sampled at the flip-flops 16 and 17 during the pulses of the second clock signal phi.sub.2.
The operation of the circuit in FIG. 6 follows the transition diagram of FIG. 1 as follows:
1. When the reset signal R is asserted, the D latches 11, 12, 14, and 15 and the flip-flops 16 and 17 are reset, their outputs go to low. The reset signal also sets the D latches 10 and 13, their outputs go to high. Consequently, the circuit enters state A.
2. If the input signal I.sub.1 is asserted while the circuit is in state A and the reset signal R is low, the output of the logic circuit 19 goes high and the outputs of logic circuits 18 and 20 go low. At the next pulse of the clock phi.sub.1, D latch 10 goes low and D latch 11 goes high. Consequently the circuit enters state B. If, on the other hand, the input signal I.sub.1 is low, the output of logic circuit 18 goes high, and that of the logic circuits 19 and 20 go low. Therefore, at the arrival of the next clock pulse, D latch 10 remains high and D latches 11 and 12 remain low. In other words, the circuit remains in state A.
The analysis for the cases where the circuit is in state B or C is similar.
For the prior art circuit in FIG. 6, the state of the circuit immediately before the clock stops is maintained because the D latches 10-15 and the flip-flops 16 and 17 maintain their values even in the absence of clock signals phi.sub.1 and phi.sub.2. Therefore, unless the circuit must respond to the input, it is possible to decrease the current consumption of the circuit by stopping the clock signal and entering a waiting state. When the clock is stopped the current consumed by the circuit is only the leakage current through insulating films or layers with very high resistance. Therefore, the current consumption is much less than that during the operation of the clock.
Because of the configuration of the prior art circuit, the signal value holding circuits 30 and 31 are necessary when the power consumption is to be decreased by stopping the clock. If the signal value holding circuits 30 and 31 were not installed, the output terminals of the transfer gates 26 and 27 would eventually enter a floating state due to leakage of current through the insulating films and PN junctions or crosstalk with other signal lines. In such circumstances, the circuit may malfunction or DC current may flow through the MOS gate at the stage preceding the transfer gate. Several kinds of signal value holding circuits are known in the prior art as shown in FIGS. 7 or 8. The use of any of these signal value holding circuits adversely affects the size, price and reliability of the digital circuit.